Computer & Digital Awareness Module
Hardware Architecture, CPU & Memory Hierarchy
Computer hardware architecture is organized around the classical Von Neumann model, comprising the Central Processing Unit (CPU), primary memory, input/output peripherals, and secondary storage. The CPU executes instructions via the fetch-decode-execute cycle using the Arithmetic Logic Unit (ALU), Control Unit (CU), and high-speed internal registers. The memory hierarchy balances access speed, cost, and storage capacity: ultra-fast CPU registers and SRAM-based cache memory sit at the apex, followed by volatile primary RAM (DRAM), non-volatile ROM, and secondary storage like Solid State Drives (SSDs). Understanding byte storage scales (KB to TB) and bus interfaces is essential for computing literacy.
Key Concepts & Examination Highlights
- The Von Neumann architecture, proposed in 1945 by mathematician John von Neumann, stores both program instructions and data in the same shared physical memory.
- The CPU contains three primary functional units: the Arithmetic Logic Unit (ALU) for mathematical/logical computations, the Control Unit (CU) for sequencing, and Registers for high-speed temporary storage.
- Cache memory, constructed using fast Static RAM (SRAM), bridges the speed disparity between the fast CPU and the slower Dynamic RAM (DRAM) main memory.
- Data storage measurement units scale by powers of 2 in binary computing: 1 Byte = 8 bits, 1 Kilobyte (KB) = 1,024 Bytes, 1 Megabyte (MB) = 1,024 KB, and 1 Gigabyte (GB) = 1,024 MB.
Curriculum & Reference Sources: IEEE Computer Society, ACM Computing Curricula, and standard computer organization references (Patterson & Hennessy).